128Mb: x16 Mobile SDRAM
Features
Mobile SDRAM
MT48H8M16LF - 2 Meg x 16 x 4 banks
Features
Figure 1:
• VDD/VDDQ = 1.70–1.95V
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal pipelined operation; column address can be
changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, or 8
• Auto precharge and concurrent auto precharge
modes
• Auto refresh and self refresh mode
• 64ms, 4,096-cycle refresh
• LVTTL-compatible inputs and outputs
• Partial-array self refresh (PASR) power-saving mode
• Deep power-down mode
• Programmable output drive strength
• On-chip temperature sensor to control the selfrefresh rate
• Operating temperature ranges
– Commercial (0°C to +70°C)
– Industrial (–40°C to +85°C)
Options
1
2
3
A
VSS
DQ15
B
DQ14
C
7
8
9
VSSQ
VDDQ
DQ0
VDD
DQ13
VDDQ
VSSQ
DQ2
DQ1
DQ12
DQ11
VSSQ
VDDQ
DQ4
DQ3
D
DQ10
DQ9
VDDQ
VSSQ
DQ6
DQ5
E
DQ8
DNU
VSS
VDD
LDQM
DQ7
F
UDQM
CLK
CKE
CAS#
RAS#
WE#
G
NC
A11
A9
BA0
BA1
CS#
H
A8
A7
A6
A0
A1
A10
J
VSS
A5
A4
A3
A2
VDD
Table 1:
5
6
Address Table
8 Meg x 16
H
2 Meg x 16 x 4 banks
4K
4K (A0–A11)
4 (BA0, BA1)
512 (A0–A8)
Configuration
Refresh count
Row addressing
Bank addressing
Column addressing
8M16
B4
-75
-8
Table 2:
Key Timing Parameters
CL = CAS (READ) latency
none
IT
:J
Speed
Grade
-75
-8
PDF: 09005aef8237e877/Source: 09005aef8237e8d8
128Mb_x16 Mobile SDRAM_Y25M_1.fm - Rev. C 2/07 EN
4
Top View
(Ball Down)
Marking
• VDD/VDDQ
– 1.8V/1.8V
• Configurations
– 8 Meg x 16 (2 Meg x 16 x 4 banks)
• Package/Ball out
– 54-ball VFBGA, 8mm x 8mm
• Timing (cycle time)
– 7.5ns @ CL = 3 (133 MHz)
– 8ns @ CL = 3 (125 MHz)
• Operating temperature
– Commercial (0°C to +70°C)
– Industrial (–40°C to +85°C)
• Die revision designator
54-Ball VFBGA Assignment
(Top View)
1
Clock
Frequency
CL = 2
CL = 3
104
MHz
83
MHz
133
MHz
125
MHz
Access Time
Setup Hold
CL = 2 CL = 3 Time Time
8ns
6ns
2.5ns
1ns
8ns
7ns
2.5ns
1ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
128Mb: x16 Mobile SDRAM
Table of Contents
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Burst Length (BL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Burst Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
CAS Latency (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Write Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Extended Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Temperature-Compensated Self Refresh (TCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Partial-Array Self Refresh (PASR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Driver Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
COMMAND INHIBIT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
NO OPERATION (NOP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
LOAD MODE REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
ACTIVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
BURST TERMINATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
AUTO REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Deep Power-Down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Bank/Row Activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
READs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
WRITEs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Deep Power-Down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Clock Suspend. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Burst Read/Single Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Concurrent Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
READ with Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
WRITE with Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
PDF: 09005aef8237e877/Source: 09005aef8237e8d8
128Mb_x16_Mobile SDRAMTOC.fm - Rev. C 2/07 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
128Mb: x16 Mobile SDRAM
List of Figures
List of Figures
Figure 1:
(Top View)
Figure 2:
Figure 3:
Figure 4:
Figure 5:
Figure 6:
Figure 7:
Figure 8:
Figure 9:
Figure 10:
Figure 11:
Figure 12:
Figure 13:
Figure 14:
Figure 15:
Figure 16:
Figure 17:
Figure 18:
Figure 19:
Figure 20:
Figure 21:
Figure 22:
Figure 23:
Figure 24:
Figure 25:
Figure 26:
Figure 27:
Figure 28:
Figure 29:
Figure 30:
Figure 31:
Figure 32:
Figure 33:
Figure 34:
Figure 35:
Figure 36:
Figure 37:
Figure 38:
Figure 39:
Figure 40:
Figure 41:
Figure 42:
Figure 43:
Figure 44:
Figure 45:
Figure 46:
Figure 47:
Figure 48:
Figure 49:
54-Ball VFBGA Assignment
1
Part Numbering Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
8 Meg x 16 SDRAM Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Extended Mode Register Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Activating a Specific Row in a Specific Bank Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Meeting tRCD (MIN) When 2 < tRCD (MIN)/tCK< 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
READ Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Consecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Random READ Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
READ-to-WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
READ-to-WRITE with Extra Clock Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
READ-to-PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Terminating a READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
WRITE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
WRITE-to-WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Random WRITE Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
WRITE-to-READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
WRITE-to-PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Terminating a WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
PRECHARGE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Clock Suspend During WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Clock Suspend During READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
READ With Auto Precharge Interrupted by a READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
READ With Auto Precharge Interrupted by a WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
WRITE With Auto Precharge Interrupted by a READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
WRITE With Auto Precharge Interrupted by a WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Typical Self Refresh Current vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Initialize and Load Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Clock Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Auto Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Self Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
READ – Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
READ – With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Single READ – Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Single READ – With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Alternating Bank Read Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
READ – DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
WRITE – Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
WRITE – With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Single WRITE – Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Single WRITE – With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Alternating Bank Write Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Write – DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
54-Ball VFBGA (8mm x 8mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
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128Mb_x16_Mobile SDRAMLOF.fm - Rev. C 2/07 EN
3
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©2006 Micron Technology, Inc. All rights reserved.
128Mb: x16 Mobile SDRAM
List of Tables
List of Tables
Table 1:
Table 2:
Table 3:
Table 4:
Table 5:
Table 6:
Table 7:
Table 8:
Table 9:
Table 10:
Table 11:
Table 12:
Table 13:
Table 14:
Table 15:
Table 16:
Table 17:
Address Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Key Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Ball Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Burst Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Truth Table 1 – Commands and DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Truth Table 2 – CKE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Truth Table 3 – Current State Bank n, Command to Bank n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Truth Table 4 – Current State Bank n, Command to Bank m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
DC Electrical Characteristics and Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Electrical Characteristics and Recommended AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . .39
AC Functional Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
IDD Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
IDD7 – Self Refresh Current Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Target Normal Output Drive Characteristics (Full-Drive Strength) . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Target Reduced Output Drive Characteristics (One-Half Drive Strength). . . . . . . . . . . . . . . . . . . . . . .45
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128Mb_x16_Mobile SDRAMLOT.fm - Rev. C 2/07 EN
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©2006 Micron Technology, Inc. All rights reserved.
128Mb: x16 Mobile SDRAM
General Description
Figure 2:
Part Numbering Diagram
Example Part Number: MT48H8M16LFB4-8 IT
–
MT48
VDD/
VDDQ
Configuration
Package
Speed
Temp.
Operating Temp.
VDD/VDDQ
1.8/1.8V
H
None
Commercial
IT
Industrial
Configuration
8 Meg x16
8M16LF
Speed Grade
Package
54-ball VFBGA (8mm x 8mm) Pb-free
-75
7.5ns
-8
8ns
B4
General Description
The Micron® 128Mb SDRAM is a high-speed CMOS, dynamic random-access memory
containing 134,217,728 bits. It is internally configured as a quad-bank DRAM with a
synchronous interface (all signals are registered on the positive edge of the clock signal,
CLK). Each of the x16’s 33,554,432-bit banks is organized as 4,096 rows by 512 columns
by 16 bits.
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select
the bank; A0–A11select the row). The address bits registered coincident with the READ
or WRITE command are used to select the starting column location for the burst access.
The SDRAM provides for programmable read or write burst lengths (BL) of 1, 2, 4, or 8
locations with a burst terminate option. An auto precharge function may be enabled to
provide a self-timed row precharge that is initiated at the end of the burst sequence.
The 128Mb SDRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it
also allows the column address to be changed on every clock cycle to achieve a highspeed, fully random access. Precharging one bank while accessing one of the other three
banks will hide the precharge cycles and provide seamless high-speed, random-access
operation.
The 128Mb SDRAM is designed to operate in 1.8V, low-power memory systems. An auto
refresh mode is provided, along with a power-saving, deep power-down mode. All
inputs and outputs are LVTTL-compatible.
Self refresh mode offers temperature compensation through an on-die temperature
sensor and partial-array self refresh (PASR). PASR allows users to achieve additional
power savings over normal usage. The temperature sensor is enabled by default and the
PASR settings can be programmed through the extended mode register.
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128Mb_x16 Mobile SDRAM_Y25M_2.fm - Rev. C 2/07 EN
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128Mb: x16 Mobile SDRAM
General Description
SDRAMs offer substantial advances in DRAM operating performance, including the
ability to synchronously burst data at a high data rate with automatic column-address
generation, the ability to interleave between internal banks in order to hide precharge
time and the capability to randomly change column addresses on each clock cycle
during a burst access.
Figure 3:
8 Meg x 16 SDRAM Functional Block Diagram
BA1
0
0
1
1
CKE
BA0
0
1
0
1
Bank
0
1
2
3
CLK
COMMAND
DECODE
CS#
WE#
CAS#
RAS#
CONTROL
LOGIC
BANK3
BANK2
BANK1
MODE REGISTER
REFRESH 12
COUNTER
12
ROWADDRESS
MUX
12
12
BANK0
ROWADDRESS
LATCH
&
DECODER
4096
BANK0
MEMORY
ARRAY
(4,096 x 512 x 16)
2
LDQM,
UDQM
SENSE AMPLIFIERS
16
4096
I/O GATING
DQM MASK LOGIC
READ DATA LATCH
WRITE DRIVERS
2
A0–A11,
BA0, BA1
14
ADDRESS
REGISTER
2
BANK
CONTROL
LOGIC
DATA
OUTPUT
REGISTER
16
16
512
(x16)
2
DQ0–
DQ15
DATA
INPUT
REGISTER
COLUMN
DECODER
9
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128Mb_x16 Mobile SDRAM_Y25M_2.fm - Rev. C 2/07 EN
COLUMNADDRESS
COUNTER/
LATCH
9
6
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128Mb: x16 Mobile SDRAM
General Description
Table 3:
Ball Descriptions
54-BALL FBGA
SYMBOL
TYPE
DESCRIPTION
F2
CLK
Input
F3
CKE
Input
G9
CS#
Input
F7, F8, F9
CAS#, RAS#,
WE#
LDQM,
UDQM
Input
Clock: CLK is driven by the system clock. All SDRAM input signals are
sampled on the positive edge of CLK. CLK also increments the internal
burst counter and controls the output registers.
Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal.
Deactivating the clock provides PRECHARGE power-down and SELF
REFRESH operation (all banks idle), ACTIVE power-down (row active in
any bank), deep power-down (all banks idle), or CLOCK SUSPEND
operation (burst/access in progress). CKE is synchronous except after the
device enters power-down and self refresh modes, where CKE becomes
asynchronous until after exiting the same mode. The input buffers,
including CLK, are disabled during power-down and self refresh modes,
providing low standby power. CKE may be tied HIGH.
Chip select: CS# enables (registered LOW) and disables (registered HIGH)
the command decoder. All commands are masked when CS# is registered
HIGH. CS# provides for external bank selection on systems with multiple
banks. CS# is considered part of the command code.
Command inputs: CAS#, RAS#, and WE# (along with CS#) define the
command being entered.
Input/Output mask: DQM is sampled HIGH and is an input mask signal for
write accesses and an output enable signal for read accesses. Input data is
masked during a WRITE cycle. The output buffers are placed in a High-Z
state (two-clock latency) during a READ cycle. LDQM corresponds to DQ0–
DQ7, UDQM corresponds to DQ8–DQ15. LDQM and UDQM are considered
same state when referenced as DQM. DQM loading is designed to match
that of DQ balls.
Bank address input(s): BA0 and BA1 define to which bank the ACTIVE,
READ, WRITE, or PRECHARGE command is being applied. These balls also
select between the mode register and the extended mode register.
E8, F1
Input
G7, G8
BA0, BA1
Input
H7, H8, J8, J7, J3, J2, H3,
H2, H1, G3, H9, G2
A0–A11
Input
A8, B9, B8, C9, C8, D9,
D8, E9, E1, D2, D1, C2,
C1, B2, B1, A2
E2, G1
DQ0–DQ15
I/O
DNU/NC
–
A7, B3, C7, D3
A3, B7, C3, D7
A9, E7, J9
A1, E3, J1
VDDQ
VSSQ
VDD
VSS
Supply
Supply
Supply
Supply
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128Mb_x16 Mobile SDRAM_Y25M_2.fm - Rev. C 2/07 EN
Address inputs: Provide the row address for ACTIVE commands, and the
column address and auto precharge bit (A10) for READ or WRITE
commands, to select one location out of the memory array in the
respective bank. During a PRECHARGE command, A10 determines
whether the PRECHARGE applies to one bank (A10 LOW, bank selected by
BA0, BA1) or all banks (A10 HIGH). The address inputs also provide the opcode during a LOAD MODE REGISTER command.
Data input/output: Data bus.
DNU = do not use: Must be left unconnected.
NC = no connect (internally unconnected): Can be left unconnected, but it
is recommended that it is connected to VSS.
DQ power: Provide isolated power to DQs for improved noise immunity.
DQ ground: Provide isolated ground to DQs for improved noise immunity.
Core power supply.
Ground.
7
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128Mb: x16 Mobile SDRAM
Functional Description
Functional Description
In general, the 128Mb SDRAMs (2 Meg x 16 x 4 banks) are quad-bank DRAMs that
operate at 1.8V and include a synchronous interface (all signals are registered on the
positive edge of the clock signal, CLK). Each of the x16’s 33,554,432-bit banks is organized as 4,096 rows by 512 columns by 16 bits.
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be accessed (BA0 and BA1
select the bank, A0–A11 select the row). The address bits (A0–A8) registered coincident
with the READ or WRITE command are used to select the starting column location for
the burst access.
Prior to normal operation, the SDRAM must be initialized. The following sections
provide detailed information covering device initialization, register definition,
command descriptions, and device operation.
Initialization
SDRAMs must be powered up and initialized in a predefined manner. Operational
procedures other than those specified may result in undefined operation. Power should
be applied to VDD and VDDQ simultaneously. Once the power is applied to VDD and
VDDQ, and the clock is stable (stable clock is defined as a signal cycling within timing
constraints specified for the clock pin), the SDRAM requires a 100µs delay prior to
issuing any command other than a COMMAND INHIBIT or NOP. Starting at some point
during this 100µs period and continuing at least through the end of this period,
COMMAND INHIBIT or NOP commands should be applied.
Once the 100µs delay has been satisfied with at least one COMMAND INHIBIT or NOP
command having been applied, a PRECHARGE command should be applied. All banks
must then be precharged, thereby placing the device in the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles must be performed. After the AUTO
REFRESH cycles are complete, the SDRAM is ready for mode register programming.
Because the mode register will power up in an unknown state, it should be loaded prior
to applying any operational command.
Mode Register Definition
There are two mode registers in the mobile component, the mode register and the
extended mode register. The mode register is illustrated in Figure 4 on page 9 and the
extended mode register is illustrated in Figure 6 on page 12.
The mode register defines the specific mode of operation of the SDRAM, including BL,
burst type, CAS latency (CL), operating mode, and write burst mode. The mode register
is programmed via the LOAD MODE REGISTER command and will retain the stored
information until it is programmed again or the device loses power.
Mode register bits M0–M2 specify BL, M3 specifies the type of burst (sequential or interleaved), M4–M6 specify the CL, M7 and M8 specify the operating mode, M9 specifies the
write burst mode, and M10, and M11 should be set to zero. M12 and M13 should be set
to zero to select the mode register.
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128Mb: x16 Mobile SDRAM
Mode Register Definition
The mode register must be loaded when all banks are idle, and the controller must wait
t
MRD before initiating the subsequent operation. Violating either of these requirements
will result in unspecified operation.
Figure 4:
Mode Register Definition
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1
A0
Address Bus
M13 M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 M0
13
0
9
8
7
6 5
4
12 11 10
0 Reserved1 WB OP Mode CAS Latency
0
3
2
1
BT Burst Length
Mode
Register (Mx)
Burst Length
M13 M12 Mode Register Definintion
0
0
Base mode register
M2 M1 M0
M3 = 0
M3 = 1
0
1
Reserved
0
0
0
1
1
1
0
Extended mode register
0
0
1
2
2
1
1
Reserved
0
1
0
4
4
0
1
1
8
M9
Write Burst Mode
1
0
0
Reserved
8
Reserved
0
Programmed burst length
1
0
1
Reserved
Reserved
1
Single location access
1
1
0
Reserved
Reserved
1
1
1
Reserved
Reserved
M8 M7
M6–M0
Operating Mode
Normal operation
0
0
Defined
–
–
–
All other states reserved
M6 M5 M4
Notes:
M3
CAS Latency
0
0
0
Reserved
0
0
1
Reserved
0
1
0
2
0
1
1
3
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
Burst Type
0
Sequential
1
Interleaved
1. Must be programmed “0,0” to ensure compatibility with future devices.
Burst Length (BL)
Read and write accesses to the SDRAM are burst oriented, with BL being programmable,
as shown in Figure 4. BL determines the maximum number of column locations that can
be accessed for a given READ or WRITE command. BLs of 1, 2, 4, or 8 locations are available for both the sequential and the interleaved burst types.
Reserved states should not be used, as unknown operation or incompatibility with
future versions may result.
When a READ or WRITE command is issued, a block of columns equal to BL is selected.
All accesses for that burst take place within this block, meaning that the burst will wrap
within the block if a boundary is reached. The block is uniquely selected by A1–A8 when
BL = 2; by A2–A8 when BL = 4; and by A3–A8 when BL = 8. The remaining (least significant) address bit(s) is (are) used to select the starting location within the block.
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128Mb: x16 Mobile SDRAM
Mode Register Definition
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved;
this is referred to as the burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by BL, the burst type, and the
starting column address, as shown in Table 4 on page 10.
Table 4:
Burst Definition
Note 1
Order of Accesses Within a
Burst
Burst
Length
Starting Column Address
22
43
84
Notes:
A1
0
0
1
1
A1
0
0
1
1
0
0
1
1
A2
0
0
0
0
1
1
1
1
A0
0
1
A0
0
1
0
1
A0
0
1
0
1
0
1
0
1
Type =
Sequential
Type =
Interleaved
0-1
1-0
0-1
1-0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
1. Whenever a boundary of the block is reached within a given sequence above, the following
access wraps within the block.
2. For BL = 2, A1–A8 select the block-of-two burst; A0 selects the starting column within the
block.
3. For BL = 4, A2–A8 select the block-of-four burst; A0–A1 select the starting column within
the block.
4. For BL = 8, A3–A8 select the block-of-eight burst; A0–A2 select the starting column within
the block.
CAS Latency (CL)
The CL is the delay, in clock cycles, between the registration of a READ command and
the availability of the first piece of output data. The latency can be set to two or three
clocks.
If a READ command is registered at clock edge n, and the latency is m clocks, the data
will be available by clock edge n + m. The DQs will start driving as a result of the clock
edge one cycle earlier (n + m - 1), and provided that the relevant access times are met,
the data will be valid by clock edge n + m. For example, assuming that the clock cycle
time is such that all relevant access times are met, if a READ command is registered at T0
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128Mb: x16 Mobile SDRAM
Mode Register Definition
and the latency is programmed to two clocks, the DQs will start driving after T1 and the
data will be valid by T2, as shown in Figure 5. Table 5 indicates the operating frequencies
at which each CL setting can be used.
Reserved states should not be used as unknown operation or incompatibility with future
versions may result.
Figure 5:
CAS Latency
T0
T1
T2
T3
READ
NOP
NOP
CLK
COMMAND
tLZ
tOH
DOUT
DQ
tAC
CL = 2
T0
T1
T2
T3
T4
READ
NOP
NOP
NOP
CLK
COMMAND
tLZ
tOH
DOUT
DQ
tAC
CL = 3
DON’T CARE
UNDEFINED
Operating Mode
The normal operating mode is selected by setting M7 and M8 to zero; the other combinations of values for M7 and M8 are reserved for future use. The programmed BL applies
to both read and write bursts.
Reserved states should not be used because unknown operation or incompatibility with
future versions may result.
Write Burst Mode
When M9 = 0, BL programmed via M0–M2 applies to both READ and WRITE bursts;
when M9 = 1, the programmed BL applies to READ bursts, but write accesses are singlelocation accesses.
Extended Mode Register
The extended mode register controls the functions beyond those controlled by the mode
register. These additional functions are special features of the mobile device. They
include temperature-compensated self refresh (TCSR) control, PASR, and output drive
strength.
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128Mb: x16 Mobile SDRAM
Mode Register Definition
The extended mode register is programmed via the MODE REGISTER SET command
(with BA1 = 1 and BA0 = 0) and retains the stored information until it is programmed
again or the device loses power.
The extended mode register must be loaded when all banks are idle and no bursts are in
progress, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements will result in unspecified operation.
Figure 6:
Extended Mode Register Diagram
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
E13
E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 E0
13
12 11 10
Register Select
9
8
7
6
All must be set to “0”
E13 E12 Mode Register Definintion
0 Base Mode Register
0
1 Reserved
0
0 Extended mode register
1
1 Reserved
1
E4
0
5
4
3
1
TCSR
DS
2
1
PASR
0
Extended Mode
Register (Ex)
E3 Maximum Case Temp
1
1
85°C
0
0
70°C
0
1
45°C
1
0
15°C
E6 E5 Driver Strength
Notes:
Address Bus
0 Full strength
E2
0
0
E1
0
0
E0
0
1
Self Refresh Coverage
Four banks2
Two banks
0
1 Half strength
1
0 Quarter strength
0
1
0
One bank
1
1 Reserved
0
1
1
1
1
0
0
1
1
0
1
0
Reserved
Reserved
1/2 bank
1/4 bank
1
1
1
Reserved
1. On-die temperature sensor is used in place of the TCSR. Setting these bits has no effect.
Temperature-Compensated Self Refresh (TCSR)
On this version of the Mobile SDR SDRAM, a temperature sensor is implemented for
automatic control of the self refresh oscillator on the device. Therefore, it is recommended not to program or use the temperature-compensated self refresh control bits in
the extended mode register.
Programming of the TCSR bits has no effect on the device. The self refresh oscillator will
continue refresh at the factory programmed optimal rate for the device temperature.
Partial-Array Self Refresh (PASR)
For further power savings during SELF REFRESH, the PASR feature allows the controller
to select the amount of memory that will be refreshed during SELF REFRESH. The
following refresh options are available:
1. All banks (banks 0, 1, 2, and 3).
2. Two banks (banks 0 and 1; BA1 = 0)
3. One bank (bank 0; BA1 = BA0 = 0)
4. Half bank (bank 0, BA1 = BA0 = row address MSB = 0)
5. Quarter bank (bank0, BA1 = BA0 = row address MSB = row address MSB - 1 = 0)
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Mode Register Definition
WRITE and READ commands occur to any bank selected during standard operation, but
only the selected banks, or segments of banks, in PASR will be refreshed during SELF
REFRESH. It is important to note that data in unused banks, or portions of banks, will be
lost when PASR is used.
Driver Strength
Bits E5 and E6 of the extended mode register can be used to select the driver strength of
the DQ outputs. This value should be set according to the application’s requirements.
Full drive strength is suitable to drive higher load systems. Half drive strength is
intended for multi-drop systems with various loads. Quarter drive strength is intended
for lighter loads or point-to-point systems.
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128Mb: x16 Mobile SDRAM
Commands
Commands
Truth Table 1 provides a quick reference of available commands. This is followed by a
written description of each command. Three additional Truth Tables appear following
“Operation” on page 17; these tables provide current state/next state information.
Table 5:
Truth Table 1 – Commands and DQM Operation
Note 1; notes appear below table
Name (Function)
CS#
COMMAND INHIBIT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
BURST TERMINATE or deep power-down
(Enter deep power-down mode)
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH
(Enter self refresh mode)
LOAD MODE REGISTER/LOAD EXTENDED MODE
REGISTER
Write enable/output enable
Write inhibit/output High-Z
Notes:
RAS# CAS#
WE#
DQM
ADDR
DQs
Notes
H
L
L
L
L
L
X
H
L
H
H
H
X
H
H
L
L
H
X
H
H
H
L
L
X
X
X
L/H
L/H
X
X
X
Bank/Row
Bank/Col
Bank/Col
X
X
X
X
X
Valid
X
2
3
3
4, 5
L
L
L
L
H
L
L
H
X
X
Bank, A10
X
X
X
6
7, 8
L
L
L
L
X
Op-Code
X
9
X
X
X
X
X
X
X
X
L
H
X
X
Active
High-Z
10
10
1. CKE is HIGH for all commands shown except SELF REFRESH and deep power-down.
2. A0–A11 provide row address, and BA0, BA1 determine which bank is made active.
3. A0–A8 provide column address; A10 HIGH enables the auto precharge feature (non persistent), while A10 LOW disables the auto precharge feature; BA0, BA1 determine which bank
is being read from or written to.
4. This command is BURST TERMINATE when CKE is HIGH and deep power-down when CKE is
LOW.
5. The purpose of the BURST TERMINATE command is to stop a data burst, thus the command
could coincide with data on the bus. However, the DQs column reads a “Don’t Care” state
to illustrate that the BURST TERMINATE command can occur when there is no data present.
6. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are “Don’t Care.”
7. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
8. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except
for CKE.
9. A0-A11 define op-code written to mode register.
10. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock
delay). LDQM controls DQ0–7, UDQM controls DQ8–15.
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Commands
COMMAND INHIBIT
The COMMAND INHIBIT function prevents new commands from being executed by the
SDRAM, regardless of whether the CLK signal is enabled. The SDRAM is effectively deselected. Operations already in progress are not affected.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to perform a NOP to an SDRAM which is
selected (CS# is LOW). This prevents unwanted commands from being registered during
idle or wait states. Operations already in progress are not affected.
LOAD MODE REGISTER
The mode register is loaded via inputs A0–A11, BA0, BA1. See “Mode Register Definition” on page 8. The LOAD MODE REGISTER and LOAD EXTENDED MODE REGISTER
commands can only be issued when all banks are idle, and a subsequent executable
command cannot be issued until tMRD is met.
ACTIVE
The ACTIVE command is used to open (or activate) a row in a particular bank for a
subsequent access. The value on the BA0, BA1 inputs selects the bank, and the address
provided on inputs A0–A11 selects the row. This row remains active (or open) for
accesses until a precharge command is issued to that bank. A PRECHARGE command
must be issued before opening a different row in the same bank.
READ
The READ command is used to initiate a burst read access to an active row. The value on
the BA0, BA1 inputs selects the bank, and the address provided on inputs A0–A8 selects
the starting column location. The value on input A10 determines whether or not auto
precharge is used. If auto precharge is selected, the row being accessed will be
precharged at the end of the read burst; if auto precharge is not selected, the row will
remain open for subsequent accesses. Read data appears on the DQ subject to the logic
level on the DQM inputs 2 clocks earlier. If a given DQM signal was registered HIGH, the
corresponding DQ will be High-Z two clocks later; if the DQM signal was registered
LOW, the DQ will provide valid data.
WRITE
The WRITE command is used to initiate a burst write access to an active row. The value
on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0–A8
selects the starting column location. The value on input A10 determines whether or not
auto precharge is used. If auto precharge is selected, the row being accessed will be
precharged at the end of the write burst; if auto precharge is not selected, the row will
remain open for subsequent accesses. Input data appearing on the DQ is written to the
memory array subject to the DQM input logic level appearing coincident with the data.
If a given DQM signal is registered LOW, the corresponding data will be written to
memory; if the DQM signal is registered HIGH, the corresponding data inputs will be
ignored, and a write will not be executed to that byte/column location.
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128Mb: x16 Mobile SDRAM
Commands
PRECHARGE
The PRECHARGE command is used to deactivate the open row in a particular bank or
the open row in all banks. The bank(s) will be available for a subsequent row access a
specified time (tRP) after the PRECHARGE command is issued. Input A10 determines
whether one or all banks are to be precharged, and in the case where only 1 bank is to be
precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as “Don’t
Care.” Once a bank has been precharged, it is in the idle state and must be activated
prior to any READ or WRITE commands being issued to that bank.
Auto Precharge
Auto precharge is a feature which performs the same individual-bank precharge function described above, without requiring an explicit command. This is accomplished by
using A10 to enable auto precharge in conjunction with a specific READ or WRITE
command. A precharge of the bank/row that is addressed with the READ or WRITE
command is automatically performed upon completion of the READ or WRITE burst.
Auto precharge is non persistent because it is either enabled or disabled for each individual READ or WRITE command.
Auto precharge ensures that the precharge is initiated at the earliest valid stage within a
burst. The user must not issue another command to the same bank until the precharge
time (tRP) is completed. This is determined as if an explicit PRECHARGE command was
issued at the earliest possible time, as described for each burst type in “Operation” on
page 17.
BURST TERMINATE
The BURST TERMINATE command is used to truncate fixed-length bursts. The most
recently registered READ or WRITE command prior to the BURST TERMINATE
command will be truncated, as shown in “Operation” on page 17.
AUTO REFRESH
AUTO REFRESH is used during normal operation of the SDRAM and is analogous to
CAS#-BEFORE-RAS# (CBR) refresh in conventional DRAMs. This command is nonpersistent, so it must be issued each time a refresh is required. All active banks must be
PRECHARGED prior to issuing an AUTO REFRESH command. The AUTO REFRESH
command should not be issued until the minimum tRP has been met after the
PRECHARGE command as shown in “Operation” on page 17.
The addressing is generated by the internal refresh controller. This makes the address
bits “Don’t Care” during an AUTO REFRESH command. The 128Mb SDRAM requires
4,096 AUTO REFRESH cycles every 64ms (tREF). Providing a distributed AUTO
REFRESH command every 15.625µs will meet the refresh requirement and ensure that
each row is refreshed. Alternatively, 4,096 AUTO REFRESH commands can be issued in a
burst at the minimum cycle rate (tRFC), once every 64ms.
SELF REFRESH
The SELF REFRESH command can be used to retain data in the SDRAM, even if the rest
of the system is powered down, as long as power is not completely removed from the
SDRAM. When in the self refresh mode, the SDRAM retains data without external
clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command
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Operation
except CKE is disabled (LOW). Once the SELF REFRESH command is registered, all the
inputs to the SDRAM become “Don’t Care” with the exception of CKE, which must
remain LOW.
During self refresh, the device is refreshed as identified in the extended mode register
(see PASR setting). The SDRAM must remain in self refresh mode for a minimum period
equal to tRAS and may remain in self refresh mode for an indefinite period beyond that.
The procedure for exiting self refresh requires a sequence of commands. First, CLK must
be stable (stable clock is defined as a signal cycling within timing constraints specified
for the clock pin) prior to CKE going back HIGH. Once CKE is HIGH, the SDRAM must
have NOP commands issued (a minimum of two clocks) for tXSR because time is
required for the completion of any internal refresh in progress.
Upon exiting the self refresh mode, AUTO REFRESH commands should be issued at
once and then every 15.625µs or less, as both SELF REFRESH and AUTO REFRESH
utilize the row refresh counter.
Deep Power-Down
Deep power-down is an operating mode used to achieve maximum power reduction by
eliminating the power to the memory array. Data will not be retained once the device
enters deep power-down mode.
This mode is entered by having all banks idle then CS# and WE# held LOW with RAS#
and CAS# held HIGH at the rising edge of the clock, while CKE is LOW. This mode is
exited by asserting CKE HIGH.
Operation
Bank/Row Activation
Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row
in that bank must be “opened.” This is accomplished via the ACTIVE command, which
selects both the bank and the row to be activated (see Figure 7 on page 18).
After opening a row (issuing an ACTIVE command), a READ or WRITE command may be
issued to that row, subject to the tRCD specification. tRCD (MIN) should be divided by
the clock period and rounded up to the next whole number to determine the earliest
clock edge after the ACTIVE command on which a READ or WRITE command can be
entered. For example, a tRCD specification of 20ns with a 125 MHz clock (8ns period)
results in 2.5 clocks, rounded to 3. This is reflected in Figure 8 on page 18, which covers
any case where 2 < tRCD (MIN)/tCK ≤ 3. (The same procedure is used to convert other
specification limits from time units to clock cycles.)
A subsequent ACTIVE command to a different row in the same bank can only be issued
after the previous active row has been “closed” (precharged). The minimum time
interval between successive ACTIVE commands to the same bank is defined by tRC.
A subsequent ACTIVE command to another bank can be issued while the first bank is
being accessed, which results in a reduction of total row-access overhead. The
minimum time interval between successive ACTIVE commands to different banks is
defined by tRRD.
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Operation
Figure 7:
Activating a Specific Row in a Specific Bank Register
CLK
CKE
HIGH
CS#
RAS#
CAS#
WE#
ROW
ADDRESS
A0–A10, A11
BANK
ADDRESS
BA0, BA1
DON’T CARE
Figure 8:
Meeting tRCD (MIN) When 2 < tRCD (MIN)/tCK< 3
T0
T1
T2
NOP
NOP
T3
T4
CLK
COMMAND
ACTIVE
READ or
WRITE
tRCD
DON’T CARE
READs
READ bursts are initiated with a READ command, as shown in Figure 9 on page 19.
The starting column and bank addresses are provided with the READ command, and
auto precharge is either enabled or disabled for that burst access. If auto precharge is
enabled, the row being accessed is precharged at the completion of the burst. For the
generic READ commands used in the following illustrations, auto precharge is disabled.
During READ bursts, the valid data-out element from the starting column address will
be available following the CL after the READ command. Each subsequent data-out
element will be valid by the next positive clock edge. Figure 5 on page 11, shows general
timing for each possible CL setting.
Upon completion of a burst, assuming no other commands have been initiated, the DQ
will go High-Z.
Data from any READ burst may be truncated with a subsequent READ command, and
data from a fixed-length READ burst may be immediately followed by data from a READ
command. In either case, a continuous flow of data can be maintained. The first data
element from the new burst follows either the last element of a completed burst or the
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Operation
last desired data element of a longer burst that is being truncated. The new READ
command should be issued x cycles before the clock edge at which the last desired data
element is valid, where x = CL - 1.
This is shown in Figure 10 on page 20 for CAS latencies of two and three; data element n
+ 3 is either the last of a burst of four or the last desired of a longer burst. The 128Mb
SDRAM uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch architecture. A READ command can be initiated on any clock cycle
following a previous READ command. Full-speed random read accesses can be
performed to the same bank, as shown in Figure 11 on page 21, or each subsequent
READ may be performed to a different bank.
Data from any READ burst may be truncated with a subsequent WRITE command, and
data from a fixed-length READ burst may be immediately followed by data from a
WRITE command (subject to bus turnaround limitations). The WRITE burst may be
initiated on the clock edge immediately following the last (or last desired) data element
from the READ burst, provided that I/O contention can be avoided. In a given system
design, there may be a possibility that the device driving the input data will go Low-Z
before the SDRAM DQ go High-Z. In this case, at least a single-cycle delay should occur
between the last read data and the WRITE command.
Figure 9:
READ Command
CLK
CKE
HIGH
CS#
RAS#
CAS#
WE#
A0–A8
COLUMN
ADDRESS
A9, A11
ENABLE AUTO PRECHARGE
A10
DISABLE AUTO PRECHARGE
BA0, BA1
BANK
ADDRESS
DON’T CARE
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Operation
Figure 10:
Consecutive READ Bursts
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
READ
ADDRESS
BANK,
COL n
NOP
NOP
NOP
NOP
READ
NOP
X = 1 cycle
BANK,
COL b
DOUT
n
DQ
DOUT
n+2
DOUT
n+1
DOUT
n+3
DOUT
b
CL = 2
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
READ
ADDRESS
BANK,
COL n
NOP
NOP
READ
NOP
NOP
NOP
NOP
X = 2 cycles
BANK,
COL b
DOUT
n
DQ
DOUT
n+1
DOUT
n+2
DOUT
n+3
DOUT
b
CL = 3
TRANSITIONING DATA
Notes:
DON’T CARE
1. Each READ command may be to any bank. DQM is LOW.
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Operation
Figure 11:
Random READ Accesses
T0
T1
T2
T3
T4
T5
CLK
COMMAND
READ
READ
READ
READ
ADDRESS
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
DOUT
n
DQ
NOP
NOP
DOUT
x
DOUT
a
DOUT
m
CL = 2
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
READ
READ
READ
READ
ADDRESS
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
NOP
DOUT
n
DQ
NOP
DOUT
a
DOUT
x
NOP
DOUT
m
CL = 3
TRANSITIONING DATA
Notes:
DON’T CARE
1. Each READ command may be to any bank. DQM is LOW.
The DQM input is used to avoid I/O contention, as shown in Figure 12 and Figure 13 on
page 22. The DQM signal must be asserted (HIGH) at least 2 clocks prior to the WRITE
command (DQM latency is 2 clocks for output buffers) to suppress data-out from the
READ. Once the WRITE command is registered, the DQ will go High-Z (or remain HighZ), regardless of the state of the DQM signal, provided the DQM was active on the clock
just prior to the WRITE command that truncated the READ command. If not, the second
WRITE will be an invalid WRITE. For example, if DQM was LOW during T4 in Figure 14
on page 23, then the WRITEs at T5 and T7 would be valid, while the WRITE at T6 would
be invalid.
The DQM signal must be de-asserted prior to the WRITE command (DQM latency is
zero clocks for input buffers) to ensure that the written data is not masked. Figure 13
shows the case where the clock frequency allows for bus contention to be avoided
without adding a NOP cycle, and Figure 13 shows the case where the additional NOP is
needed. A fixed-length READ burst may be followed by, or truncated with, a
PRECHARGE command to the same bank (provided that auto precharge was not activated). The PRECHARGE command should be issued x cycles before the clock edge at
which the last desired data element is valid, where x = CL - 1. This is shown in Figure 14
for each possible CL; data element n + 3 is either the last of a burst of four or the last
desired of a longer burst. Following the PRECHARGE command, a subsequent
command to the same bank cannot be issued until tRP is met. Note that part of the row
precharge time is hidden during the access of the last data element(s).
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Operation
In the case of a fixed-length burst being executed to completion, a PRECHARGE
command issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length burst with auto precharge. The disadvantage of the PRECHARGE command is that it requires that the command and address
buses be available at the appropriate time to issue the command; the advantage of the
PRECHARGE command is that it can be used to truncate fixed-length bursts.
Figure 12:
READ-to-WRITE
T0
T1
T2
T3
T4
CLK
DQM
COMMAND
READ
ADDRESS
BANK,
COL n
NOP
NOP
NOP
WRITE
BANK,
COL b
tCK
tHZ
DOUT n
DQ
DIN b
tDS
TRANSITIONING DATA
Notes:
Figure 13:
DON’T CARE
1. CL = 3 is used for illustration; the READ command may be to any bank, and the WRITE command may be to any bank. If a burst of one is used, then DQM is not required.
READ-to-WRITE with Extra Clock Cycle
T0
T1
T2
T3
T4
T5
CLK
DQM
COMMAND
READ
ADDRESS
BANK,
COL n
NOP
NOP
NOP
NOP
WRITE
BANK,
COL b
tHZ
DOUT n
DQ
DIN b
tDS
TRANSITIONING DATA
Notes:
DON’T CARE
1. CL = 3 is used for illustration; the READ command may be to any bank, and the WRITE command may be to any bank.
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Operation
Figure 14:
READ-to-PRECHARGE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
t RP
COMMAND
READ
NOP
NOP
NOP
PRECHARGE
NOP
NOP
ACTIVE
X = 1 cycle
ADDRESS
BANK
(a or all)
BANK a,
COL n
DOUT
n+2
DOUT
n+1
DOUT
n
DQ
BANK a,
ROW
DOUT
n+3
CL = 2
T0
T1
T2
T3
T4
T5
T6
T7
CLK
t RP
COMMAND
READ
NOP
NOP
NOP
PRECHARGE
NOP
NOP
ACTIVE
X = 2 cycles
ADDRESS
BANK
(a or all)
BANK a,
COL n
DOUT
n+2
DOUT
n+1
DOUT
n
DQ
BANK a,
ROW
DOUT
n+3
CL = 3
TRANSITIONING DATA
Notes:
Figure 15:
DON’T CARE
1. DQM is LOW.
Terminating a READ Burst
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
READ
ADDRESS
BANK,
COL n
NOP
NOP
NOP
BURST
TERMINATE
NOP
NOP
X = 1 cycle
DOUT
n
DQ
DOUT
n+2
DOUT
n+1
DOUT
n+3
CL = 2
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
READ
ADDRESS
BANK,
COL n
NOP
NOP
NOP
BURST
TERMINATE
NOP
NOP
NOP
X = 2 cycles
DOUT
n
DQ
DOUT
n+1
DOUT
n+2
DOUT
n+3
CL = 3
TRANSITIONING DATA
Notes:
DON’T CARE
1. DQM is LOW.
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128Mb: x16 Mobile SDRAM
Operation
Fixed-length READ bursts may be truncated with a BURST TERMINATE command,
provided that auto precharge was not activated. The BURST TERMINATE command
should be issued x cycles before the clock edge at which the last desired data element is
valid, where x = CL - 1. This is shown in Figure 15 for each possible CL; data element n +
3 is the last desired data element of a longer burst.
WRITEs
WRITE bursts are initiated with a WRITE command, as shown in Figure 16.
The starting column and bank addresses are provided with the WRITE command, and
auto precharge is either enabled or disabled for that access. If auto precharge is enabled,
the row being accessed is precharged at the completion of the burst. For the generic
WRITE commands used in the following illustrations, auto precharge is disabled.
During WRITE bursts, the first valid data-in element will be registered coincident with
the WRITE command. Subsequent data elements will be registered on each successive
positive clock edge. Upon completion of a fixed-length burst, assuming no other
commands have been initiated, the DQ will remain High-Z and any additional input
data will be ignored (see Figure 17 on page 25).
Figure 16:
WRITE Command
CLK
CKE
HIGH
CS#
RAS#
CAS#
WE#
A0–A8
COLUMN
ADDRESS
A9, A11
ENABLE AUTO PRECHARGE
A10
DISABLE AUTO PRECHARGE
BA0, BA1
BANK
ADDRESS
VALID ADDRESS
DON’T CARE
Data for any WRITE burst may be truncated with a subsequent WRITE command, and
data for a fixed-length WRITE burst may be immediately followed by data for a WRITE
command. The new WRITE command can be issued on any clock following the previous
WRITE command, and the data provided coincident with the new command applies to
the new command. An example is shown in Figure 18 on page 25. Data n + 1 is either the
last of a burst of two or the last desired of a longer burst. The Mobile SDRAM uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch
architecture. A WRITE command can be initiated on any clock cycle following a previous
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128Mb: x16 Mobile SDRAM
Operation
WRITE command. Full-speed random write accesses within a page can be performed to
the same bank, as shown in Figure 19, or each subsequent WRITE may be performed to
a different bank.
Figure 17:
WRITE Burst
T0
T1
T2
T3
COMMAND
WRITE
NOP
NOP
NOP
ADDRESS
BANK,
COL n
CLK
DQ
DIN
n
DIN
n+1
TRANSITIONING DATA
Notes:
Figure 18:
DON’T CARE
1. BL = 2. DQM is LOW.
WRITE-to-WRITE
T0
T1
T2
COMMAND
WRITE
NOP
WRITE
ADDRESS
BANK,
COL n
CLK
DQ
DIN
n
BANK,
COL b
DIN
n+1
DIN
b
DON’T CARE
Notes:
1. DQM is LOW. Each WRITE command may be to any bank.
Data for any WRITE burst may be truncated with a subsequent READ command, and
data for a fixed-length WRITE burst may be immediately followed by a READ command.
Once the READ command is registered, the data inputs will be ignored, and WRITEs will
not be executed. An example is shown in Figure 20 on page 26. Data n + 1 is either the
last of a burst of two or the last desired of a longer burst.
Data for a fixed-length WRITE burst may be followed by, or truncated with, a
PRECHARGE command to the same bank (provided that auto precharge was not activated). The PRECHARGE command should be issued tWR after the clock edge at which
the last desired input data element is registered. The auto precharge mode requires a
t
WR of at least one clock plus time, regardless of frequency.
In addition, when truncating a WRITE burst, the DQM signal must be used to mask
input data for the clock edge prior to, and the clock edge coincident with, the
PRECHARGE command. An example is shown in Figure 21 on page 27. Data n + 1 is
either the last of a burst of two or the last desired of a longer burst. Following the
PRECHARGE command, a subsequent command to the same bank cannot be issued
until tRP is met.
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128Mb: x16 Mobile SDRAM
Operation
In the case of a fixed-length burst being executed to completion, a PRECHARGE
command issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length burst with auto precharge. The disadvantage of the PRECHARGE command is that it requires that the command and address
buses be available at the appropriate time to issue the command; the advantage of the
PRECHARGE command is that it can be used to truncate fixed-length bursts.
Fixed-length WRITE bursts can be truncated with the BURST TERMINATE command.
When truncating a WRITE burst, the input data applied coincident with the BURST
TERMINATE command will be ignored. The last data written (provided that DQM is
LOW at that time) will be the input data applied one clock previous to the BURST
TERMINATE command. This is shown in Figure 22 on page 27, where data n is the last
desired data element of a longer burst.
Figure 19:
Random WRITE Cycles
T0
T1
T2
T3
COMMAND
WRITE
WRITE
WRITE
WRITE
ADDRESS
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
DIN
n
DIN
a
DIN
x
DIN
m
CLK
DQ
DON’T CARE
Notes:
Figure 20:
1. Each WRITE command may be to any bank. DQM is LOW.
WRITE-to-READ
T0
T1
T2
T3
T4
T5
COMMAND
WRITE
NOP
READ
NOP
NOP
NOP
ADDRESS
BANK,
COL n
DOUT
b
DOUT
b+1
CLK
DQ
DIN
n
BANK,
COL b
DIN
n+1
DON’T CARE
Notes:
1. CL = 2 is used for illustration; the WRITE command may be to any bank, and the READ command may be to any bank. DQM is LOW.
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Operation
Figure 21:
WRITE-to-PRECHARGE
T0
T1
T2
T3
WRITE
NOP
PRECHARGE
NOP
T4
T5
T6
NOP
ACTIVE
NOP
CLK
tWR @ tCK 15ns
DQM
t RP
COMMAND
BANK
(a or all)
BANK a,
COL n
ADDRESS
BANK a,
ROW
t WR
DIN
n
DQ
DIN
n+1
tWR @ tCK < 15ns
DQM
t RP
COMMAND
WRITE
NOP
NOP
PRECHARGE
BANK
(a or all)
BANK a,
COL n
ADDRESS
NOP
NOP
ACTIVE
BANK a,
ROW
t WR
DIN
n
DQ
DIN
n+1
DON’T CARE
Notes:
Figure 22:
1. DQM could remain LOW in this example if the WRITE burst is a fixed length of two.
Terminating a WRITE Burst
T0
T1
T2
COMMAND
WRITE
BURST
TERMINATE
ADDRESS
BANK,
COL n
(ADDRESS)
DIN
n
(DATA)
CLK
DQ
TRANSITIONING DATA
Notes:
NEXT
COMMAND
DON’T CARE
1. DQMs are LOW.
PRECHARGE
The PRECHARGE command (see Figure 23 on page 28) is used to deactivate the open
row in a particular bank or the open row in all banks. The bank(s) will be available for a
subsequent row access some specified time (tRP) after the PRECHARGE command is
issued. Input A10 determines whether one or all banks are to be precharged, and in the
case where only one bank is to be precharged, inputs BA0, BA1 select the bank. When all
banks are to be precharged, inputs BA0, BA1 are treated as “Don’t Care.” Once a bank
has been precharged, it is in the idle state and must be activated prior to any READ or
WRITE commands being issued to that bank.
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128Mb: x16 Mobile SDRAM
Operation
Figure 23:
PRECHARGE Command
CLK
CKE
HIGH
CS#
RAS#
CAS#
WE#
A0–A9, A11
All Banks
A10
Bank Selected
BANK
ADDRESS
BA0, BA1
DON’T CARE
VALID ADDRESS
Power-Down
Power-down occurs if CKE is registered LOW coincident with a NOP or COMMAND
INHIBIT when no accesses are in progress. If power-down occurs when all banks are
idle, this mode is referred to as precharge power-down; if power-down occurs when
there is a row active in any bank, this mode is referred to as active power-down. Entering
power-down deactivates the input and output buffers, excluding CKE, for maximum
power savings while in standby. The device must not remain in the power-down state
longer than the refresh period (64ms) since no refresh operations are performed in this
mode.
The power-down state is exited by registering a NOP or COMMAND INHIBIT and CKE
HIGH at the desired clock edge (meeting tCKS). See Figure 24 on page 28.
Figure 24:
Power-Down
((
))
((
))
CLK
tCKS
CKE
COMMAND
> tCKS
((
))
((
))
((
))
NOP
NOP
ACTIVE
tRCD
All banks idle
Input buffers gated off
Enter power-down mode.
Exit power-down mode.
tRAS
tRC
DON’T CARE
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Operation
Deep Power-Down
Deep power-down mode is a maximum power savings feature achieved by shutting off
the power to the entire memory array of the device. Data in the memory array will not be
retained once deep power-down mode is executed. Deep power-down mode is entered
by having all banks idle then CS# and WE# held LOW with RAS# and CAS# HIGH at the
rising edge of the clock, while CKE is LOW. CKE must be held LOW during deep powerdown.
In order to exit deep power-down mode, CKE must be asserted HIGH. Upon exit of deep
power-down mode a full Mobile SDRAM initialization sequence, is required.
Clock Suspend
The clock suspend mode is entered when a column access/burst is in progress and CKE
is registered LOW. In the clock suspend mode, the internal clock is deactivated,
“freezing” the synchronous logic.
For each positive clock edge on which CKE is sampled LOW, the next internal positive
clock edge is suspended. Any command or data present on the input balls at the time of
a suspended internal clock edge is ignored; any data present on the DQ balls remains
driven; and burst counters are not incremented, as long as the clock is suspended. (See
examples in Figure 25 and Figure 26 on page 30.)
Clock suspend mode is exited by registering CKE HIGH; the internal clock and related
operation will resume on the subsequent positive clock edge.
Figure 25:
Clock Suspend During WRITE Burst
T0
T1
NOP
WRITE
T2
T3
T4
T5
NOP
NOP
DIN
n+1
DIN
n+2
CLK
CKE
INTERNAL
CLOCK
COMMAND
ADDRESS
DIN
BANK,
COL n
DIN
n
DON’T CARE
Notes:
1. BL = 4 or greater, and DM is LOW.
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Operation
Figure 26:
Clock Suspend During READ Burst
T0
T1
T2
T3
T4
T5
T6
CLK
CKE
INTERNAL
CLOCK
COMMAND
READ
ADDRESS
BANK,
COL n
DQ
NOP
NOP
NOP
DOUT
n
DOUT
n+1
NOP
DOUT
n+2
NOP
DOUT
n+3
DON’T CARE
Notes:
1. CL = 2, BL = 4 or greater, and DQM is LOW.
Burst Read/Single Write
The burst read/single write mode is entered by programming the write burst mode bit
(M9) in the mode register to a logic 1. In this mode, all WRITE commands result in the
access of a single column location (burst of one), regardless of the programmed BL.
READ commands access columns according to the programmed BL and sequence, just
as in the normal mode of operation (M9 = 0).
Concurrent Auto Precharge
Micron SDRAM devices support concurrent auto precharge, which allows an access
command (READ or WRITE) to another bank while an access command with auto
precharge enabled is executing. Four cases where concurrent auto precharge occurs are
defined below.
READ with Auto Precharge
1. Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a READ on bank n, 2 or 3 clocks later, depending on CL. The precharge to bank n
will begin when the READ to bank m is registered (see Figure 27 on page 31).
2. Interrupted by a WRITE (with or without auto precharge): When a WRITE to bank m
registers, a READ on bank n will be interrupted. DQM should be used 2 clocks prior to
the WRITE command to prevent bus contention. The precharge to bank n will begin
when the WRITE to bank m is registered (see Figure 28 on page 31).
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Operation
Figure 27:
READ With Auto Precharge Interrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
NOP
BANK n
Internal
States
READ - AP
BANK n
Page Active
NOP
READ - AP
BANK m
READ with Burst of 4
NOP
NOP
NOP
NOP
Interrupt Burst, Precharge
Idle
t RP - BANK n
Page Active
BANK m
Precharge
READ with Burst of 4
BANK n,
COL a
ADDRESS
tRP - BANK m
BANK m,
COL d
DOUT
a+1
DOUT
a
DQ
CL = 3 (BANK
DOUT
d
DOUT
d+1
n)
CL = 3 (BANK m)
DON’T CARE
Notes:
Figure 28:
1. DQM is LOW.
READ With Auto Precharge Interrupted by a WRITE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
BANK n
Internal
States
READ - AP
BANK n
Page
Active
NOP
NOP
NOP
READ with Burst of 4
WRITE - AP
BANK m
NOP
NOP
Interrupt Burst, Precharge
Idle
tRP - BANK n
Page Active
BANK m
ADDRESS
NOP
Write-Back
WRITE with Burst of 4
BANK n,
COL a
t WR - BANK m
BANK m,
COL d
1
DQM
DOUT
a
DQ
DIN
d
DIN
d+1
DIN
d+2
DIN
d+3
CL = 3 (BANK n)
DON’T CARE
Notes:
1. DQM is HIGH at T2 to prevent DOUT a + 1 from contending with DIN d at T4.
WRITE with Auto Precharge
1. Interrupted by a READ (with or without auto precharge): When a READ to bank m
registers, it will interrupt a WRITE on bank n, with the data-out appearing 2 or 3
clocks later, depending on CL. The precharge to bank n will begin after tWR is met,
where tWR begins when the READ to bank m is registered. The last valid WRITE to
bank n will be data-in registered one clock prior to the READ to bank m (see
Figure 29).
2. Interrupted by a WRITE (with or without auto precharge): When a WRITE to bank m
registers, it will interrupt a WRITE on bank n. The precharge to bank n will begin after
t
WR is met, where tWR begins when the WRITE to bank m is registered. The last valid
data WRITE to bank n will be data registered one clock prior to a WRITE to bank m
(see Figure 30 on page 32).
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Operation
Figure 29:
WRITE With Auto Precharge Interrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
BANK n
Internal
States
NOP
WRITE - AP
BANK n
Page Active
NOP
READ - AP
BANK m
WRITE with Burst of 4
Page Active
BANK m
DIN
a
DQ
NOP
NOP
Interrupt Burst, Write-Back
Precharge
tWR - BANK n
tRP - BANK n
NOP
tRP - BANK m
READ with Burst of 4
BANK n,
COL a
ADDRESS
NOP
BANK m,
COL d
DOUT
d+1
DOUT
d
DIN
a+1
CL = 3 (BANK m)
DON’T CARE
Notes:
Figure 30:
1. DQM is LOW.
WRITE With Auto Precharge Interrupted by a WRITE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
BANK n
NOP
WRITE - AP
BANK n
Page Active
NOP
NOP
WRITE with Burst of 4
WRITE - AP
BANK m
NOP
Interrupt Burst, Write-Back
Internal
States
tWR - BANK n
BANK m
ADDRESS
DQ
Page Active
NOP
Precharge
tRP - BANK n
t WR - BANK m
Write-Back
WRITE with Burst of 4
BANK n,
COL a
DIN
a
NOP
BANK m,
COL d
DIN
a+1
DIN
a+2
DIN
d
DIN
d+1
DIN
d+2
DIN
d+3
DON’T CARE
Notes:
1. DQM is LOW.
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Truth Tables
Truth Tables
Table 6:
Truth Table 2 – CKE
Notes: 1–4; notes appear below table
CKEn-1
CKEn
Current State
Commandn
Actionn
L
L
Power-Down
Self refresh
Clock suspend
Deep power-down
Power-Down
Deep power-down
Self refresh
Clock suspend
All banks idle
All banks idle
All banks idle
Reading or Writing
X
X
X
X
COMMAND INHIBIT or NOP
X
COMMAND INHIBIT or NOP
X
COMMAND INHIBIT or NOP
BURST TERMINATE
AUTO REFRESH
VALID
See Truth Table 3
Maintain power-down
Maintain self refresh
Maintain clock suspend
Maintain deep power-down
Exit power-down
Exit deep power-down
Exit self refresh
Exit clock suspend
Power-Down entry
Deep power-down entry
Self refresh entry
Clock suspend entry
L
H
H
L
H
H
Notes:
Notes
5
6
5
7
8
5
1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous
clock edge.
2. Current state is the state of the SDRAM immediately prior to clock edge n.
3. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of COMMANDn.
4. All states and sequences not shown are illegal or reserved.
5. Deep power-down is a power-saving feature of this Mobile SDRAM device. This command is
BURST TERMINATE when CKE is HIGH and deep power-down when CKE is LOW.
6. Exiting power-down at clock edge n will put the device in the all banks idle state in time for
clock edge n + 1 (provided that tCKS is met).
7. Exiting self refresh at clock edge n will put the device in the all banks idle state once tXSR is
met. COMMAND INHIBIT or NOP commands should be issued on any clock edges occurring
during the tXSR period. A minimum of two NOP commands must be provided during tXSR
period.
8. After exiting clock suspend at clock edge n, the device will resume operation and recognize
the next command at clock edge n + 1.
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Truth Tables
Table 7:
Truth Table 3 – Current State Bank n, Command to Bank n
Notes: 1–6; notes appear below table
Current State
CS#
RAS#
CAS#
WE#
Any
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
H
L
L
L
L
H
H
L
H
H
L
H
H
H
L
H
X
H
H
L
L
H
L
L
H
L
L
H
H
L
L
H
H
X
H
H
H
L
L
H
L
L
H
L
L
L
H
L
L
L
Idle
Row active
Read (auto
precharge
disabled)
Write (auto
precharge
disabled)
Notes:
Command (Action)
COMMAND INHIBIT (NOP/Continue previous operation)
NO OPERATION (NOP/Continue previous operation)
ACTIVE (Select and activate row)
AUTO REFRESH
LOAD MODE REGISTER
PRECHARGE
READ (Select column and start READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE (Deactivate row in bank or banks)
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE (Truncate READ burst, start PRECHARGE)
BURST TERMINATE
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE (Truncate WRITE burst, start PRECHARGE)
BURST TERMINATE
Notes
7
7
8
9
9
10
9
9
10
11
9
9
10
11
1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Truth Table 2) and after
tXSR has been met (if the previous state was self refresh).
2. This table is bank-specific, except where noted; i.e., the current state is for a specific bank
and the commands shown are those allowed to be issued to that bank when in that state.
Exceptions are covered in the notes below.
3. Current state definitions:
The bank has been precharged, and tRP has been met.
A row in the bank has been activated, and tRCD has been met. No data
bursts/accesses and no register accesses are in progress.
Read:
A READ burst has been initiated, with auto precharge disabled, and has
not yet terminated or been terminated.
Write:
A WRITE burst has been initiated, with auto precharge disabled, and has
not yet terminated or been terminated.
4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP commands, or allowable commands to the other bank should be
issued on any clock edge occurring during these states. Allowable commands to the other
bank are determined by its current state and Truth Table 3, and according to Truth Table 4.
Idle:
Row active:
Precharging:
Starts with registration of a PRECHARGE command and ends when
is met. Once tRP is met, the bank will be in the idle state.
Starts with registration of an ACTIVE command and ends when tRCD
is met. Once tRCD is met, the bank will be in the row active state.
Starts with registration of a READ command with auto precharge
enabled and ends when tRP has been met. Once tRP is met, the bank
will be in the idle state.
Starts with registration of a WRITE command with auto precharge
enabled and ends when tRP has been met. Once tRP is met, the bank
will be in the idle state.
tRP
Row activating:
Read w/auto
precharge enabled:
Write w/auto
precharge enabled:
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Truth Tables
5. The following states must not be interrupted by any executable command; COMMAND
INHIBIT or NOP commands must be applied on each positive clock edge during these states.
Refreshing:
6.
7.
8.
9.
10.
11.
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Starts with registration of an AUTO REFRESH command and ends
when tRFC is met. Once tRFC is met, the SDRAM will be in the all
banks idle state.
Accessing mode
Starts with registration of a LOAD MODE REGISTER command and
register:
ends when tMRD has been met. Once tMRD is met, the SDRAM will
be in the all banks idle state.
Precharging all:
Starts with registration of a PRECHARGE ALL command and ends
when tRP is met. Once tRP is met, all banks will be in the idle state.
All states and sequences not shown are illegal or reserved.
Not bank-specific; requires that all banks are idle.
Does not affect the state of the bank and acts as a NOP to that bank.
READs or WRITEs listed in the Command (Action) column include READs or WRITEs with
auto precharge enabled and READs or WRITEs with auto precharge disabled.
May or may not be bank-specific; if all banks are to be precharged, all must be in a valid
state for precharging.
Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regardless of bank.
35
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Truth Tables
Table 8:
Truth Table 4 – Current State Bank n, Command to Bank m
Notes: 1–6; notes appear below and on next page
Current State
CS#
RAS#
CAS#
WE#
Any
H
L
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
H
X
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
X
H
X
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
X
H
X
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
Idle
Row
Activating,
Active, or
Precharging
Read
(Auto
Precharge
Disabled)
Write
(Auto
Precharge
Disabled)
Read
(With Auto
Precharge)
Write
(With Auto
Precharge)
Notes:
Command (Action)
COMMAND INHIBIT (NOP/Continue previous operation)
NO OPERATION (NOP/Continue previous operation)
Any command allowed to bank m
ACTIVE (Select and activate row)
READ (Select column and start READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE
Notes
7
7
7, 8
7, 9
10
7, 11
7, 12
10
7, 13, 14
7, 13, 15
10
7, 13, 16
7, 13, 17
10
1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Truth Table 2) and after
tXSR has been met (if the previous state was self refresh).
2. This table describes alternate bank operation, except where noted; i.e., the current state is
for bank n and the commands shown are those allowed to be issued to bank m (assuming
that bank m is in such a state that the given command is allowable). Exceptions are covered
in the notes below.
3. Current state definitions:
Idle:
Row active:
Read:
Write:
Read w/auto
precharge enabled:
Write w/auto
precharge enabled:
The bank has been precharged, and tRP has been met.
A row in the bank has been activated, and tRCD has been met. No
data bursts/accesses and no register accesses are in progress.
A READ burst has been initiated, with auto precharge disabled, and
has not yet terminated or been terminated.
A WRITE burst has been initiated, with auto precharge disabled, and
has not yet terminated or been terminated.
Starts with registration of a READ command with auto precharge
enabled, and ends when tRP has been met. Once tRP is met, the
bank will be in the idle state.
Starts with registration of a WRITE command with auto precharge
enabled, and ends when tRP has been met. Once tRP is met, the
bank will be in the idle state.
4. AUTO REFRESH, SELF REFRESH, and LOAD MODE REGISTER commands may only be issued
when all banks are idle.
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Truth Tables
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank
represented by the current state only.
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs to bank m listed in the Command (Action) column include READs or
WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled.
8. For a READ without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the READ on bank n, CL later (see Figure 10 on
page 20).
9. For a READ without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the READ on bank n when registered (see
Figure 12 and Figure 13 on page 22). DQM should be used one clock prior to the WRITE
command to prevent bus contention.
10. Burst in bank n continues as initiated.
11. For a WRITE without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the WRITE on bank n when registered (see
Figure 20 on page 26), with the data-out appearing CL later. The last valid WRITE to bank n
will be data-in registered one clock prior to the READ to bank m.
12. For a WRITE without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the WRITE on bank n when registered (see
Figure 18 on page 25). The last valid WRITE to bank n will be data-in registered one clock
prior to the READ to bank m.
13. Concurrent auto precharge: Bank n will initiate the auto precharge command when its
burst has been interrupted by bank m’s burst.
14. For a READ with auto precharge interrupted by a READ (with or without auto precharge),
the READ to bank m will interrupt the READ on bank n, CL later (see Figure 27 on page 31).
The PRECHARGE to bank n will begin when the READ to bank m is registered.
15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge),
the WRITE to bank m will interrupt the READ on bank n when registered (see Figure 28 on
page 31). DQM should be used two clocks prior to the WRITE command to prevent bus contention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered.
16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge),
the READ to bank m will interrupt the WRITE on bank n when registered, with the data-out
appearing CL later (see Figure 29 on page 32). The PRECHARGE to bank n will begin after
tWR is met, where tWR begins when the READ to bank m is registered. The last valid WRITE
bank n will be data-in registered one clock prior to the READ to bank m.
17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge),
the WRITE to bank m will interrupt the WRITE on bank n when registered. The PRECHARGE
to bank n will begin after tWR is met, where tWR begins when the WRITE to bank m is registered (see Figure 30 on page 32). The last valid WRITE to bank n will be data registered
one clock to the WRITE to bank m.
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Electrical Specifications
Electrical Specifications
Stresses greater than those listed in Table 9 may cause permanent damage to the device.
This is a stress rating only, and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
Table 9:
Absolute Maximum Ratings
Parameter
Voltage on VDD/VDDQ supply relative to VSS
Voltage on inputs, NC or I/O pins relative to VSS
Storage temperature (plastic)
Table 10:
Symbol
Min
Max
Units
VDD/VDDQ
VIN
TSTG
–0.35
–0.35
–55
+2.8
+2.8
+150
V
V
°C
Max
Units
Notes
DC Electrical Characteristics and Operating Conditions
Notes: 1, 5, 6; notes appear on page 42; VDD = VDDQ = 1.7–1.95V
Parameter/Condition
Symbol
Supply voltage
I/O supply voltage
Input high voltage: Logic 1; All inputs
Input low voltage: Logic 0; All inputs
Output high voltage: All inputs
Output low voltage: All inputs
Operating temperature:
Commercial
Industrial
Input leakage current:
Any input 0V ≤ VIN ≤ VDD (All other pins not under test = 0V)
Output leakage current: DQ disabled; 0V ≤ VOUT ≤ VDDQ
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38
VDD
VDDQ
VIH
VIL
VOH
VOL
TA
Min
1.7
1.95
1.7
1.95
0.8 × VDDQ VDD + 0.3
–0.3
+0.3
0.9 x VDDQ
–
–
0.2
V
V
V
V
V
V
°C
II
0
–40
–1.0
+70
+85
1.0
µA
IOZ
–1.5
1.5
µA
22
22
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Electrical Specifications
Table 11:
Electrical Characteristics and Recommended AC Operating Conditions
Notes: 5, 6, 8, 9, 11; notes appear on page 42
AC Characteristics
-75
Parameter
Access time from CLK (pos. edge)
Address hold time
Address setup time
CLK high-level width
CLK low-level width
Clock cycle time
CKE hold time
CKE setup time
CS#, RAS#, CAS#, WE#, DQM hold time
CS#, RAS#, CAS#, WE#, DQM setup time
Data-in hold time
Data-in setup time
Data-out High-Z time
Data-out Low-Z time
Data-out hold time (load)
Data-out hold time (no load)
ACTIVE-to-PRECHARGE command
ACTIVE-to-ACTIVE command period
ACTIVE-to-READ or WRITE delay
Refresh period (4,096 rows)
AUTO REFRESH period
PRECHARGE command period
ACTIVE bank a to ACTIVE bank b command
Transition time
WRITE recovery time
Exit SELF REFRESH-to-ACTIVE command
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Symbol
CL = 3
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
t
AC (3)
AC (2)
t
AH
t
AS
t
CH
t
CL
tCK (3)
tCK (2)
t
CKH
tCKS
tCMH
tCMS
tDH
tDS
tHZ (3)
tHZ (2)
tLZ
tOH
t
OHN
tRAS
tRC
tRCD
tREF
tRFC
tRP
tRRD
tT
tWR
t
XSR
t
39
-8
Min
Max
Min
Max
Units
–
–
1
2.5
3
3
7.5
9.6
1
2.5
1
2.5
1
2.5
–
–
1
2.5
1.8
45
67.5
19.2
–
75
19.2
15
0.5
15
75
6
8
–
–
–
–
100
100
–
–
–
–
–
–
6
8
–
–
–
120,000
–
–
64
–
–
–
1.2
–
–
–
–
1
2.5
3
3
8
12
1
2.5
1
2.5
1
2.5
–
–
1
2.5
1.8
48
72
24
7
8
–
–
–
–
100
100
–
–
–
–
–
–
7
8
–
–
–
120,000
–
–
64
–
–
–
1.2
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
ns
80
24
16
0.5
15
80
Notes
23
23
10
10
7
24
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Electrical Specifications
Table 12:
AC Functional Characteristics
Notes: 5, 6, 8, 9, 11; notes appear on page 42
Parameter
Symbol
READ/WRITE command to READ/WRITE command
CKE to clock disable or power-down entry mode
CKE to clock enable or power-down exit setup mode
DQM to input data delay
DQM to data mask during WRITEs
DQM to data High-Z during READs
WRITE command to input data delay
Data-in to ACTIVE command
Data-in to PRECHARGE command
Last data-in to burst STOP command
Last data-in to new READ/WRITE command
Last data-in to PRECHARGE command
LOAD MODE REGISTER command to ACTIVE or REFRESH
command
Data-out to High-Z from PRECHARGE command
Table 13:
t
-8
Units
Notes
CCD
CKED
t
PED
t
DQD
tDQM
t
DQZ
t
DWD
t
DAL
t
DPL
t
BDL
t
CDL
tRDL
tMRD
1
1
1
0
0
2
0
5
2
1
1
2
2
1
1
1
0
0
2
0
5
2
1
1
2
2
t
CK
CK
t
CK
t
CK
tCK
t
CK
t
CK
t
CK
t
CK
t
CK
t
CK
tCK
tCK
17
14
14
17
17
17
17
15, 21
16, 21
17
17
16, 21
tROH(3)
3
2
3
2
tCK
tCK
17
17
t
CL = 3
CL = 2
-75
tROH(2)
t
IDD Specifications and Conditions
Notes: 5, 6, 11, 13; notes appear on page 42; VDD = VDDQ = 1.7–1.95V
Max
Parameter/Condition
Operating current:
Active mode; BL = 1; READ or WRITE; tRC = tRC (MIN)
Standby current:
Power-down mode; All banks idle; CKE = LOW
Standby current:
Non-power-down mode; All banks idle; CKE = HIGH
Standby current:
Power-down mode; CKE = LOW; CS# = HIGH; All banks active; No
accesses in progress
Standby current:
Non-power-down mode; CKE = HIGH; CS# = HIGH; All banks active
after tRCD met; No accesses in progress
Operating current:
Burst mode; READ or WRITE; All banks active, half DQs toggling
every cycle
tRFC = tRFC (MIN)
Auto refresh current:
t
CKE = HIGH; CS# = HIGH
RFC = 15.625µs
Deep power-down
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40
Symbol
-75
-8
Units
Notes
IDD1
50
50
mA
3, 18, 19
IDD2P
150
150
µA
26
IDD2N
10
10
mA
IDD3P
5
5
mA
3, 12, 19
IDD3N
40
35
mA
3, 12, 19
IDD4
50
50
mA
3, 18, 19
IDD5
IDD6
IZZ
100
2
10
80
2
10
mA
mA
µA
3, 12, 18,
19, 25
26, 28
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Electrical Specifications
Table 14:
IDD7 – Self Refresh Current Options
Notes: 4, 27; notes appear on page 42; VDD = VDDQ = 1.70–1.95
Temperature-Compensated Self Refresh
Parameter/Condition
Self refresh current:
CKE < 0.2V – 4 banks open
Self refresh current:
CKE < 0.2V – 2 banks open
Self refresh current:
CKE < 0.2V – 1 bank open
Self refresh current:
CKE < 0.2V – 1/2 bank open
Self refresh current:
CKE < 0.2V – 1/4 bank open
Figure 31:
Maximum
Temperature
-75/-8
Units
85ºC
70ºC
45ºC
15ºC
85ºC
70ºC
45ºC
15ºC
85ºC
70ºC
45ºC
15ºC
85ºC
70ºC
45ºC
15ºC
85ºC
70ºC
45ºC
15ºC
300
220
180
160
220
180
160
150
180
160
150
145
120
110
100
90
115
105
95
90
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
Typical Self Refresh Current vs. Temperature
TBD
Table 15:
Capacitance
Note: 2; notes appear on page 42
Parameter
Input capacitance: CLK
Input capacitance: All other input-only balls
Input/Output capacitance: DQ, LDQM, UDQM
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41
Symbol
Min
Max
Units
CI1
CI2
CIO
1.5
1.5
3.0
4.0
4.0
6.0
pF
pF
pF
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Notes
Notes
1. All voltages referenced to VSS.
2. This parameter is sampled. VDD, VDDQ = +1.8V; TA = 25°C; ball under test biased at
1.4V. f = 1 MHz.
3. IDD is dependent on output loading and cycle rates. Specified values are obtained
with minimum cycle time and the outputs open.
4. When the device is in self refresh mode, the on-chip refresh oscillator and address
counters are enabled.
5. The minimum specifications are used only to indicate cycle time at which proper
operation is ensured over the full temperature range (0°C –70°C standard,
–40°C– 85°C for IT).
6. An initial pause of 100µs is required after power-up, followed by two AUTO REFRESH
commands, before proper device operation is ensured. (VDD and VDDQ must be powered up simultaneously. VSS and VSSQ must be at same potential.) The two AUTO
REFRESH command wake-ups should be repeated any time the tREF refresh requirement is exceeded.
7. AC characteristics assume tT = 1ns.
8. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner.
9. Outputs measured for 1.8V at 0.9V with equivalent load:
Q
20pF
10. tHZ defines the time at which the output achieves the open circuit condition; it is not
a reference to VOH or VOL. The last valid data element will meet tOH before going
High-Z.
11. AC timing and IDD tests have VIL and VIH, with timing referenced to VIH/2 = crossover
point. If the input transition time is longer than tT (MAX), then the timing is referenced at VIL (MAX) and VIH (MIN) and no longer at the VIH/2 crossover point.
12. Other input signals are allowed to transition no more than once every two clocks and
are otherwise at valid VIH or VIL levels.
13. IDD specifications are tested after the device is properly initialized.
14. Timing actually specified by tCKS; clock(s) specified as a reference only at minimum
cycle rate.
15. Timing actually specified by tWR plus tRP; clock(s) specified as a reference only at
minimum cycle rate.
16. Timing actually specified by tWR.
17. Required clocks are specified by JEDEC functionality and are not dependent on any
timing parameter.
18. The IDD current will increase or decrease proportionally according to the amount of
frequency alteration for the test condition.
19. Address transitions average one transition every 2 clocks.
20. CLK must be toggled a minimum of two times during this period.
21. Based on tCK = 7.5ns for -75 and tCK = 8ns for -8.
22. VIH overshoot: VIH (MAX) = VDDQ + 2V for a pulse width ≤ 3ns, and the pulse width
cannot be greater than one third of the cycle rate. VIL undershoot: VIL (MIN) = –2V for
a pulse width ≤ 3ns.
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Notes
23. The clock frequency must remain constant (stable clock is defined as a signal cycling
within timing constraints specified for the clock pin) during access or precharge
states (READ, WRITE, including tWR, and PRECHARGE commands). CKE may be
used to reduce the data rate.
24. Auto precharge mode only. The precharge timing budget (tRP) begins at 7.5ns for -75
and 7ns for -8 after the first clock delay, after the last WRITE is executed. For auto precharge mode, at least one clock cycle is required during tWR.
25. CKE is HIGH during REFRESH command period tRFC (MIN) else CKE is LOW.
26. Measurement is taken 500ms after entering into this operating mode to allow tester
measurement settling time.
27. Values for IDD7 85°C 4 bank, 2 bank, and 1 bank are guaranteed for the entire temperature range. All other IDD7 values are estimated.
28. Deep power-down current is a nominal value at 25°C. This parameter is not tested.
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Notes
Table 16:
Target Normal Output Drive Characteristics (Full-Drive Strength)
The above characteristics are specified under best and worst process variation/conditions
Pull-Down Current (mA)
Pull-Up Current (mA)
Voltage (V)
Min
Max
Min
Max
0.00
0.10
0.20
0.30
0.40
0.50
0.60
0.70
0.80
0.85
0.90
0.95
1.00
1.10
1.20
1.30
1.40
1.50
1.60
1.70
1.80
1.90
0.00
2.80
5.60
8.40
11.20
14.00
16.80
19.60
22.40
23.80
23.80
23.80
23.80
23.80
23.80
23.80
23.80
23.80
23.80
23.80
–
–
0.00
18.53
26.80
32.80
37.05
40.00
42.50
44.57
46.50
47.48
48.50
49.40
50.05
51.35
52.65
53.95
55.25
56.55
57.85
59.15
60.45
61.75
0.00
–2.80
–5.60
–8.40
–11.20
–14.00
–16.80
–19.60
–22.40
–23.80
–23.80
–23.80
–23.80
–23.80
–23.80
–23.80
–23.80
–23.80
–23.80
–23.80
–
–
0.00
–18.53
–26.80
–32.80
–37.05
–40.00
–42.50
–44.57
–46.50
–47.48
–48.50
–49.40
–50.05
–51.35
–52.65
–53.95
–55.25
–56.55
–57.85
–59.15
–60.45
–61.75
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Notes
Table 17:
Target Reduced Output Drive Characteristics (One-Half Drive Strength)
The above characteristics are specified under best and worst process variation/conditions
Pull-Down Current (mA)
Pull-Up Current (mA)
Voltage (V)
Min
Max
Min
Max
0.00
0.10
0.20
0.30
0.40
0.50
0.60
0.70
0.80
0.85
0.90
0.95
1.00
1.10
1.20
1.30
1.40
1.50
1.60
1.70
1.80
1.90
0.00
1.27
2.55
3.82
5.09
6.36
7.64
8.91
10.16
10.80
10.80
10.80
10.80
10.80
10.80
10.80
10.80
10.80
10.80
10.80
–
–
0.00
8.42
12.30
14.95
16.84
18.20
19.30
20.30
21.20
21.60
22.00
22.45
22.73
23.21
23.67
24.14
24.61
25.08
25.54
26.01
26.48
26.95
0.00
–1.27
–2.55
–3.82
–5.09
–6.36
–7.64
–8.91
–10.16
–10.80
–10.80
–10.80
–10.80
–10.80
–10.80
–10.80
–10.80
–10.80
–10.80
–10.80
–
–
0.00
–8.42
–12.30
–14.95
–16.84
–18.20
–19.30
–20.30
–21.20
–21.60
–22.00
–22.45
–22.73
–23.21
–23.67
–24.14
–24.61
–25.08
–25.54
–26.01
–26.48
–26.95
PDF: 09005aef8237e877/Source: 09005aef8237e8d8
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Timing Diagrams
Timing Diagrams
Figure 32:
Initialize and Load Mode Registers
T0
CLK
((
))
((
))
Tn + 1
T1
tCK
To + 1
Tp + 1
Tq + 1
Tr + 1
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
tCKS tCKH
CKE
((
))
((
))
COMMAND1
((
))
((
))
DQM
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
A0-A9, A11
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
CODE
((
))
((
))
CODE
((
))
((
))
VALID
((
))
((
))
A10
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
CODE
((
))
((
))
CODE
((
))
((
))
VALID
((
))
((
))
BA0, BA1
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
BA0
BA0 == L,
L,
BA1
BA1==HL
((
))
((
))
VALID
((
))
((
))
DQ
((
))
((
))
((
))
((
))
tRP
tRFC2
tCMS tCMH
NOP
((
))
((
))
PRE
AR
((
))
((
))
AR
((
))
((
))
LMR
((
))
((
))
LMR
((
))
((
))
((
))
((
))
VALID
((
))
((
))
((
))
((
))
((
))
((
))
tAS tAH
ALL BANKS
t AS tAH
tAS tAH
High-Z
BA0 = L,
BA1 = L
((
))
((
))
((
))
T = 100µs
Power-up:
VDD and
CLK stable
tRFC2
tMRD3
Load Mode
Register
Precharge
all banks
tMRD3
Load Extended
Mode Register
DON’T CARE
Notes:
1. PRE = PRECHARGE command, AR = AUTO REFRESH command, LMR = LOAD MODE REGISTER
command.
2. Only NOPs or COMMAND INHIBITs may be issued during tRFC time.
3. At least one NOP or COMMAND INHIBIT is required during tMRD time.
PDF: 09005aef8237e877/Source: 09005aef8237e8d8
128Mb_x16 Mobile SDRAM_Y25M_2.fm - Rev. C 2/07 EN
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128Mb: x16 Mobile SDRAM
Timing Diagrams
Figure 33:
Power-Down Mode
T0
T1
tCK
CLK
T2
((
))
((
))
tCL
tCKS
tCH
CKE
tCKS
PRECHARGE
Tn + 2
tCKS
((
))
tCKH
tCMS tCMH
COMMAND
Tn + 1
NOP
((
))
((
))
NOP
NOP
ACTIVE
DQM
((
))
((
))
A0–A9, A11
((
))
((
))
ROW
((
))
((
))
ROW
((
))
((
))
BANK
ALL BANKS
A10
SINGLE BANK
tAS
BA0, BA1
tAH
BANK(S)
High-Z
((
))
DQ
Two clock cycles
Input buffers gated off while in
power-down mode
Precharge all
active banks
All banks idle
All banks idle, enter
power-down mode
Exit power-down mode
DON’T CARE
Notes:
1. Violating refresh requirements during power-down may result in a loss of data.
PDF: 09005aef8237e877/Source: 09005aef8237e8d8
128Mb_x16 Mobile SDRAM_Y25M_2.fm - Rev. C 2/07 EN
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©2006 Micron Technology, Inc. All rights reserved.
128Mb: x16 Mobile SDRAM
Timing Diagrams
Figure 34:
Clock Suspend Mode
T0
T1
T2
tCK
CLK
T3
T4
T5
T6
T7
T8
T9
tCL
tCH
tCKS tCKH
CKE
tCKS
tCKH
tCMS tCMH
COMMAND
READ
NOP
NOP
NOP
NOP
NOP
WRITE
NOP
tCMS tCMH
DQM
tAS
A0–A9, A11
tAH
COLUMN m 2
tAS
COLUMN e 2
tAH
A10
tAS
BA0, BA1
tAH
BANK
BANK
tAC
tOH
tAC
DQ
DOUT m
tHZ
DOUT m + 1
tDS
tDH
DOUT e
DOUT e + 1
tLZ
DON’T CARE
UNDEFINED
Notes:
1. For this example, BL = 2, CL = 3, and auto precharge is disabled.
2. A9 and A11 are “Don’t Care.”
PDF: 09005aef8237e877/Source: 09005aef8237e8d8
128Mb_x16 Mobile SDRAM_Y25M_2.fm - Rev. C 2/07 EN
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©2006 Micron Technology, Inc. All rights reserved.
128Mb: x16 Mobile SDRAM
Timing Diagrams
Figure 35:
Auto Refresh Mode
T0
CLK
T1
tCK
T2
((
))
((
))
tCH
tCKS
tCKH
tCMS
tCMH
PRECHARGE
NOP
AUTO
REFRESH
NOP
((
))
( ( NOP
))
A0–A9, A11
ALL BANKS
A10
SINGLE BANK
tAS
DQ
To + 1
((
))
AUTO
REFRESH
NOP
((
))
((
))
DQM
BA0, BA1
((
))
((
))
((
))
CKE
COMMAND
Tn + 1
tCL
((
))
( ( NOP
))
ACTIVE
((
))
((
))
((
))
((
))
((
))
((
))
ROW
((
))
((
))
((
))
((
))
ROW
tAH
((
))
((
))
BANK(S)
High-Z
((
))
((
))
((
))
tRP
tRFC1
BANK
((
))
tRFC1
Precharge all
active banks
DON’T CARE
Notes:
1. Each AUTO REFRESH command performs a REFRESH cycle. Back-to-back commands are not
required. tRFC must not be interrupted by any executable command; COMMAND INHIBIT or
NOP must be applied on each positive edge during tRFC.
PDF: 09005aef8237e877/Source: 09005aef8237e8d8
128Mb_x16 Mobile SDRAM_Y25M_2.fm - Rev. C 2/07 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
128Mb: x16 Mobile SDRAM
Timing Diagrams
Figure 36:
Self Refresh Mode
T0
CLK
T1
tCK
tCL
tCH
T2
tCKS
Tn + 1
((
))
((
))
> tRAS
((
))
((
))
To + 2
((
))
CKE
tCKS
tCKH
tCMS
tCMH
((
))
((
))
((
))
((
))
NOP or
COMMAND INHIBIT( (
))
DQM
((
))
((
))
((
))
((
))
A0–A9, A11
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
COMMAND
PRECHARGE
NOP
ALL BANKS
A10
SINGLE BANK
tAS
BA0, BA1
DQ
To + 1
AUTO
REFRESH
tAH
BANK(S)
High-Z
((
))
((
))
tRP
Precharge all
active banks
tXSR
Enter self refresh mode
Exit self refresh mode
(Restart refresh time base)
CLK stable prior to exiting
self refresh mode
Notes:
AUTO
REFRESH
DON’T CARE
1. tXSR requires a minimum of two clocks regardless of frequency or timing.
PDF: 09005aef8237e877/Source: 09005aef8237e8d8
128Mb_x16 Mobile SDRAM_Y25M_2.fm - Rev. C 2/07 EN
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©2006 Micron Technology, Inc. All rights reserved.
128Mb: x16 Mobile SDRAM
Timing Diagrams
Figure 37:
READ – Without Auto Precharge
T0
T1
tCK
CLK
T2
T3
T4
T5
NOP
NOP
T6
T7
T8
NOP
ACTIVE
tCL
tCH
tCKS
tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
READ
NOP
PRECHARGE
tCMS tCMH
DQM
tAS
A0–A9, A11
tAS
COLUMN m2
ROW
tAH
ALL BANKS
ROW
A10
tAS
BA0, BA1
tAH
ROW
ROW
tAH
BANK
DISABLE AUTO PRECHARGE
SINGLE BANKS
BANK
BANK(S)
tAC
tOH
tAC
DOUT m
DQ
tLZ
CAS Latency
tRCD
tAC
tOH
DOUT m+1
BANK
tAC
tOH
tOH
DOUT m+2
DOUT m+3
tHZ
tRP
tRAS
tRC
DON’T CARE
UNDEFINED
Notes:
1. For this example, BL = 4, CL = 2, and the READ burst is followed by a “manual” PRECHARGE.
2. A9 and A11 are “Don’t Care.”
PDF: 09005aef8237e877/Source: 09005aef8237e8d8
128Mb_x16 Mobile SDRAM_Y25M_2.fm - Rev. C 2/07 EN
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©2006 Micron Technology, Inc. All rights reserved.
128Mb: x16 Mobile SDRAM
Timing Diagrams
Figure 38:
READ – With Auto Precharge
T0
T1
tCK
CLK
tCKS
T2
T3
T4
T5
NOP
NOP
NOP
T6
T7
T8
NOP
ACTIVE
tCL
tCH
tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
READ
tCMS
NOP
tCMH
DQM
tAS
A0–A9, A11
tAS
A10
COLUMN m 2
tAH
ROW
ENABLE AUTO PRECHARGE
ROW
tAS
BA0, BA1
tAH
ROW
ROW
tAH
BANK
BANK
BANK
tAC
tOH
tAC
DOUT m
DQ
tAC
tOH
DOUT m + 1
tAC
tOH
DOUT m + 2
DOUT m + 3
tHZ
tLZ
tRCD
tOH
tRP
CAS Latency
tRAS
tRC
DON’T CARE
UNDEFINED
Notes:
1. For this example, BL = 4 and CL = 2.
2. A9 and A11 are “Don’t Care.”
PDF: 09005aef8237e877/Source: 09005aef8237e8d8
128Mb_x16 Mobile SDRAM_Y25M_2.fm - Rev. C 2/07 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
128Mb: x16 Mobile SDRAM
Timing Diagrams
Figure 39:
Single READ – Without Auto Precharge
T0
T1
tCK
CLK
T2
T3
T4
T5
NOP 3
NOP 3
T6
T7
T8
tCL
tCH
tCKS
tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
READ
PRECHARGE
NOP
ACTIVE
NOP
tCMS tCMH
DQM
tAS
A0–A9, A11
tAS
COLUMN m2
ROW
tAH
ALL BANKS
ROW
A10
tAS
BA0, BA1
tAH
ROW
ROW
DISABLE AUTO PRECHARGE
tAH
SINGLE BANKS
BANK
BANK
BANK(S)
BANK
tOH
tAC
DOUT m
DQ
tLZ
tRCD
tHZ
CAS Latency
tRP
tRAS
tRC
DON’T CARE
UNDEFINED
Notes:
1. For this example, BL = 4, CL = 2, and the READ burst is followed by a “manual” PRECHARGE.
2. A9 and A11 are “Don’t Care.”
3. PRECHARGE command not allowed or tRAS would be violated.
PDF: 09005aef8237e877/Source: 09005aef8237e8d8
128Mb_x16 Mobile SDRAM_Y25M_2.fm - Rev. C 2/07 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
128Mb: x16 Mobile SDRAM
Timing Diagrams
Figure 40:
Single READ – With Auto Precharge
T0
T1
tCK
CLK
tCKS
T2
T3
T4
T5
T6
T7
T8
tCL
tCH
tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
NOP3
NOP3
READ
tCMS
NOP
NOP
ACTIVE
NOP
tCMH
DQM
tAS
A0–A9, A11
tAS
A10
COLUMN m2
tAH
ROW
ENABLE AUTO PRECHARGE
ROW
tAS
BA0, BA1
tAH
ROW
ROW
tAH
BANK
BANK
BANK
tAC
t OH
DOUT m
DQ
tRCD
CAS Latency
tHZ
tRP
tRAS
tRC
DON’T CARE
UNDEFINED
Notes:
1. For this example, BL = 4, CL = 2, and the READ burst is followed by a “manual” PRECHARGE.
2. A9 and A11 are “Don’t Care.”
3. PRECHARGE command not allowed or tRAS would be violated.
PDF: 09005aef8237e877/Source: 09005aef8237e8d8
128Mb_x16 Mobile SDRAM_Y25M_2.fm - Rev. C 2/07 EN
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©2006 Micron Technology, Inc. All rights reserved.
128Mb: x16 Mobile SDRAM
Timing Diagrams
Figure 41:
Alternating Bank Read Accesses
T0
T1
tCK
CLK
T2
T3
T4
T5
NOP
ACTIVE
T6
T7
T8
READ
NOP
ACTIVE
tCL
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
READ
tCMS
NOP
tCMH
DQM
tAS
A0–A9, A11
tAH
COLUMN b 2
ROW
ENABLE AUTO PRECHARGE
ROW
ENABLE AUTO PRECHARGE
ROW
tAS
BA0, BA1
COLUMN m 2
ROW
tAS
A10
tAH
ROW
ROW
tAH
BANK 0
BANK 0
BANK 3
BANK 3
tAC
tOH
tAC
DOUT m
DQ
tAC
tOH
DOUT m + 1
BANK 0
tAC
tOH
DOUT m + 2
tAC
tOH
DOUT m + 3
tAC
tOH
DOUT b
tLZ
tRCD - BANK 0
tRP - BANK 0
CAS Latency - BANK 0
tRCD - BANK 0
tRAS - BANK 0
tRC - BANK 0
tRCD - BANK 3
tRRD
CAS Latency - BANK 3
DON’T CARE
UNDEFINED
Notes:
1. For this example, BL = 4 and CL = 2.
2. A9 and A11 are “Don’t Care.”
PDF: 09005aef8237e877/Source: 09005aef8237e8d8
128Mb_x16 Mobile SDRAM_Y25M_2.fm - Rev. C 2/07 EN
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©2006 Micron Technology, Inc. All rights reserved.
128Mb: x16 Mobile SDRAM
Timing Diagrams
Figure 42:
READ – DQM Operation
T0
T1
tCK
CLK
tCKS
tCKH
tCMS
tCMH
T2
T3
T4
T5
NOP
NOP
T6
T7
T8
NOP
NOP
NOP
tCL
tCH
CKE
COMMAND
ACTIVE
NOP
READ
tCMS
NOP
tCMH
DQM
tAS
A0–A9, A11
tAS
A10
COLUMN m 2
tAH
ENABLE AUTO PRECHARGE
ROW
tAS
BA0, BA1
tAH
ROW
DISABLE AUTO PRECHARGE
tAH
BANK
BANK
tAC
tOH
DQ
tAC
DOUT m
tLZ
tRCD
tHZ
tAC
tOH
DOUT m + 2
tLZ
tOH
DOUT m + 3
tHZ
CAS Latency
DON’T CARE
UNDEFINED
Notes:
1. For this example, CL = 2.
2. A9 and A11 are “Don’t Care.”
PDF: 09005aef8237e877/Source: 09005aef8237e8d8
128Mb_x16 Mobile SDRAM_Y25M_2.fm - Rev. C 2/07 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
128Mb: x16 Mobile SDRAM
Timing Diagrams
Figure 43:
WRITE – Without Auto Precharge
T0
tCK
CLK
T1
T2
tCL
T3
T4
T5
T6
T7
T8
T9
NOP
NOP
NOP
NOP
PRECHARGE
NOP
ACTIVE
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
WRITE
tCMS tCMH
DQM
tAS
A0–A9, A11
ROW
tAH
ALL BANKS
ROW
tAS
BA0, BA1
COLUMN m 3
ROW
tAS
A10
tAH
ROW
tAH
DISABLE AUTO PRECHARGE
SINGLE BANK
BANK
BANK
BANK
tDS
tDH
DIN m
DQ
tDS
tDH
DIN m + 1
tDS
tDH
DIN m + 2
tDS
tDH
DIN m + 3
t WR 2
tRCD
tRAS
BANK
tRP
tRC
DON’T CARE
Notes:
1. For this example, BL = 4, and the WRITE burst is followed by a “manual” PRECHARGE.
2. 15ns is required between and the PRECHARGE command, regardless of frequency.
3. A9 and A11 are “Don’t Care.”
PDF: 09005aef8237e877/Source: 09005aef8237e8d8
128Mb_x16 Mobile SDRAM_Y25M_2.fm - Rev. C 2/07 EN
57
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
128Mb: x16 Mobile SDRAM
Timing Diagrams
Figure 44:
WRITE – With Auto Precharge
T0
tCK
CLK
tCKS
tCKH
tCMS
tCMH
T1
T2
tCL
T3
T4
T5
T6
T7
T8
T9
NOP
NOP
NOP
NOP
NOP
NOP
ACTIVE
tCH
CKE
COMMAND
ACTIVE
NOP
WRITE
tCMS tCMH
DQM
tAS
A0–A9, A11
tAH
ROW
ENABLE AUTO PRECHARGE
ROW
tAS
BA0, BA1
COLUMN m 2
ROW
tAS
A10
tAH
ROW
tAH
BANK
BANK
tDS
tDH
DIN m
DQ
BANK
tDS
tDH
DIN m + 1
tDS
tDH
DIN m + 2
tRCD
tRAS
tDS
tDH
DIN m + 3
tWR
tRP
tRC
DON’T CARE
Notes:
1. For this example, BL = 4.
2. A9 and A11 are “Don’t Care.”
PDF: 09005aef8237e877/Source: 09005aef8237e8d8
128Mb_x16 Mobile SDRAM_Y25M_2.fm - Rev. C 2/07 EN
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©2006 Micron Technology, Inc. All rights reserved.
128Mb: x16 Mobile SDRAM
Timing Diagrams
Figure 45:
Single WRITE – Without Auto Precharge
T0
tCK
CLK
T1
T2
tCL
T3
T4
NOP 4
NOP 4
T5
T6
T7
T8
ACTIVE
NOP
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
WRITE
PRECHARGE
NOP
tCMS tCMH
DQM
tAS
A0–A9, A11
tAH
ALL BANKS
ROW
tAS
BA0, BA1
COLUMN m 3
ROW
tAS
A10
tAH
ROW
tAH
DISABLE AUTO PRECHARGE
SINGLE BANK
BANK
BANK
BANK
tDS
BANK
tDH
DIN m
DQ
tRCD
tRAS
tRP
t WR 2
tRC
DON’T CARE
Notes:
1.
2.
3.
4.
PDF: 09005aef8237e877/Source: 09005aef8237e8d8
128Mb_x16 Mobile SDRAM_Y25M_2.fm - Rev. C 2/07 EN
For this example, BL = 1, and the WRITE burst is followed by a “manual” PRECHARGE.
15ns is required between and the PRECHARGE command, regardless of frequency.
A9 and A11 are “Don’t Care.”
PRECHARGE command not allowed or tRAS would be violated.
59
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©2006 Micron Technology, Inc. All rights reserved.
128Mb: x16 Mobile SDRAM
Timing Diagrams
Figure 46:
Single WRITE – With Auto Precharge
T0
tCK
CLK
tCKS
tCKH
tCMS
tCMH
T1
tCL
T2
T3
T4
T5
T6
T7
NOP3
WRITE
NOP
NOP
NOP
T8
T9
tCH
CKE
COMMAND
NOP3
ACTIVE
NOP3
tCMS
ACTIVE
NOP
tCMH
DQM
tAS
A0–A9, A11
tAH
ROW
ENABLE AUTO PRECHARGE
ROW
ROW
tAS
BA0, BA1
COLUMN m 2
ROW
tAS
A10
tAH
tAH
BANK
BANK
tDS
BANK
tDH
DIN m
DQ
tRCD
tRAS
tWR
tRP
tRC
DON’T CARE
Notes:
1.
2.
3.
4.
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128Mb_x16 Mobile SDRAM_Y25M_2.fm - Rev. C 2/07 EN
For this example, BL = 1, and the WRITE burst is followed by a “manual” PRECHARGE.
15ns is required between and the PRECHARGE command, regardless of frequency.
A9 and A11 are “Don’t Care.”
WRITE command not allowed or tRAS would be violated.
60
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Timing Diagrams
Figure 47:
Alternating Bank Write Accesses
T0
tCK
CLK
T1
T2
tCL
T3
T4
T5
T6
T7
T8
T9
NOP
NOP
ACTIVE
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
WRITE
tCMS
NOP
ACTIVE
NOP
WRITE
tCMH
DQM
tAS
A0–A9, A11
tAH
COLUMN b 2
ROW
ENABLE AUTO PRECHARGE
ROW
ENABLE AUTO PRECHARGE
ROW
tAS
BA0, BA1
COLUMN m 2
ROW
tAS
A10
tAH
ROW
ROW
tAH
BANK 0
BANK 0
tDS
tDH
DIN m
DQ
BANK 1
tDS
tDH
DIN m + 1
tDS
BANK 1
tDH
tDS
DIN m + 2
tDH
DIN m + 3
tDS
tDH
DIN b
tWR - BANK 0
tRCD - BANK 0
BANK 0
tDS
tDH
DIN b + 1
tRP - BANK 0
tDS
tDH
DIN b + 2
tDS
tDH
DIN b + 3
tRCD - BANK 0
tRAS - BANK 0
tRC - BANK 0
tRCD - BANK 1
tRRD
tWR - BANK 1
DON’T CARE
Notes:
1. For this example, BL = 4.
2. A9 and A11 are “Don’t Care.”
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128Mb_x16 Mobile SDRAM_Y25M_2.fm - Rev. C 2/07 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
128Mb: x16 Mobile SDRAM
Timing Diagrams
Figure 48:
Write – DQM Operation
T0
T1
tCK
CLK
T2
T3
T4
T5
NOP
NOP
NOP
T6
T7
NOP
NOP
tCL
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
WRITE
tCMS tCMH
DQM
tAS
A0–A9, A11
tAH
ENABLE AUTO PRECHARGE
ROW
tAS
BA0, BA1
COLUMN m 2
ROW
tAS
A10
tAH
tAH
DISABLE AUTO PRECHARGE
BANK
BANK
tDS
tDH
tDS
DIN m
DQ
tDH
DIN m + 2
tDS
tDH
DIN m + 3
tRCD
DON’T CARE
Notes:
1. For this example, BL = 4.
2. A9 and A11 are “Don’t Care.”
PDF: 09005aef8237e877/Source: 09005aef8237e8d8
128Mb_x16 Mobile SDRAM_Y25M_2.fm - Rev. C 2/07 EN
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128Mb: x16 Mobile SDRAM
Package Dimensions
Package Dimensions
Figure 49:
54-Ball VFBGA (8mm x 8mm)
0.65 ±0.05
SEATING PLANE
SOLDER BALL MATERIAL:
C
96.5% Sn, 3% Ag, 0.5% Cu (Lead-Free – B4)
SOLDER MASK DEFINED BALL PADS: Ø0.40
0.10 C
54X Ø0.45 ±0.05
SOLDER BALL
DIAMETER REFERS
TO POST REFLOW
CONDITION. THE PREREFLOW DIAMETER
IS 0.42.
SUBSTRATE MATERIAL: PLASTIC LAMINATE
MOLD COMPOUND: EPOXY NOVOLAC
6.40
0.80
TYP
BALL A1 ID
BALL A1 ID
BALL A1
4.00 ±0.05
BALL A9
6.40
CL
8.00 ±0.10
3.20 ±0.05
0.80 TYP
CL
3.20 ±0.05
4.00 ±0.05
1.00 MAX
8.00 ±0.10
Notes:
1. All dimensions are in millimeters.
®
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992
Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of
their respective owners.
This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range
for production devices. Although considered final, these specifications are subject to change, as further product
development and data characterization sometimes occur.
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2006 Micron Technology, Inc. All rights reserved.
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